Adaptive Digital Circuits for Power-Performance Range beyond Wide Voltage Scaling by Saurabh Jain & Longyang Lin & Massimo Alioto

Author:Saurabh Jain & Longyang Lin & Massimo Alioto
Language: eng
Format: epub
ISBN: 9783030387969
Publisher: Springer International Publishing

3.9 Automated Design Flow Extension to Thread-Level Time-Interleaved Reconfiguration

The design flow for thread-level reconfiguration in processors is relatively easier in comparison to the pipeline-level one. As fundamental difference, the effectiveness of pipeline-level reconfiguration is limited in microarchitectures whose critical path lies in feedback paths, as the latter ones cannot be re-pipelined (see Sect. 3.3 and Fig. 3.4). Similarly, pipeline-level reconfiguration has limited applicability in architectures where re-pipelining introduces architectural hazards due to data inter-dependency (e.g., some computation depends on previous computations before it is completed, and stalls need to be inserted to resolve the hazards). Indeed, in this case the resolution of architectural hazards under re-pipelining requires a change in the control flow, and hence fundamental architectural (functional) changes that are unacceptable in applications with legacy requirements (e.g., binary-code software compatibility in microprocessors). In such cases or any other case where re-pipelining is difficult, pipeline-level reconfiguration is not an option, and thread-level must be introduced as discussed below.

In thread-level reconfiguration, logic depth is reduced by inserting additional registers to enable time-interleaved operation (see Chap. 2) and bypassing them to operate as in the original microarchitecture. Under time-interleaved operation, functionally equivalent tasks are simultaneously executed on multiple incoming input streams. This in turn enables the execution of multiple microprocessor threads (i.e., independent instruction steams and creation of multiple virtual cores), or processing of multiple input channels as in the case of multi-sensor platforms, among the many other examples.

The design flow for thread-level reconfiguration in Fig. 3.1b is structurally similar to the pipeline-level reconfiguration discussed in Sects. 3.3–3.8 and is somewhat simpler as discussed in the following. As shown in Fig. 3.16, the netlist generated at Step 1 in Fig. 3.1b is parsed to identify the flip-flops by simply tracing the clock port. This step also yields the netlist graph in the form of a hash table as described in Sect. 3.4.1. All the information associated with the gates and connection is stored as a graph database. Since this step operates directly on the gate-level netlist, the flow is architecture-agnostic and applies both to proprietary IP described at the RTL level or to existing IPs available in the form of a gate-level netlist (as usual for soft IPs provided by a third party, often times in an obfuscated gate-level form). In the following, the design flow is described assuming that up to two-thread operation is enabled, being its generalization to multiple threads immediate. At Step 1, each flip-flop is replaced by two cascaded flip-flops, as required by time interleaving in Chap. 2 (or, more in general, a number of cascaded flip-flops equal to the number of simultaneous threads).

Fig. 3.16Pictorial description of the design flow in Fig. 3.1b to introduce thread-level reconfiguration via selective enablement of time interleaving in the gate-level netlist of a baseline design (e.g., processor). This diagram assumes dual-thread reconfiguration and can be readily adapted to any number of threads larger than two

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